This invention concerns a method of fabrication of a semiconductor integrated circuit device; and, more particularly, it relates to a technique that is applicable to the fabrication of a semiconductor integrated circuit device, including fabrication of semiconductor wafers.
The present inventors have conducted a search of the prior art with a view toward preventing the occurrence of obstacles extending from the edges of wafers. For example, Japanese Published Unexamined Patent Application No. 2000-68273 discloses a technique which involves polishing a metal film by a CMP method to form a pattern, and then removing any of the metal film which remains on edges of a device forming surface of the wafer by a wet etching method, laser or CMP method, thereby preventing the occurrence of obstacles extending from the edges.
Further, polishing apparatuses for polishing the edges of wafers are disclosed, for example, in Japanese Published Unexamined Patent Application Hei 11 (1999)-104942, Japanese Published Unexamined Patent Application Hei 11(1999)-90803, Japanese Published Unexamined Patent Application Hei 11 (1999)-48109, Japanese Published Unexamined Patent Application Hei 11 (1999)-33888, Japanese Published Unexamined Patent Application Hei 10(1998)-328989, Japanese Published Unexamined Patent Application Hei 10(1998)-309666, Japanese Published Unexamined Patent Application Hei 10(1998)-296641, Japanese Published Unexamined Patent Application Hei 4(1992)-34931 and Japanese Published Unexamined Patent Application Sho 64(1989)-71656.